The present invention relates generally to a computer implemented method and system for verifying a design and in particular to inserting a multitude of faults during a computer simulation to verify a system design.
Electronics play an ever more important role, for example, in today's world of automobiles. Today, electronics makes up nearly 40% of the content of an average new automobile and the share of electronics is expected to grow higher. According to one study, an average new automobile includes more than 40 electronic controllers, five miles of wiring, and more than 10 million lines of computer software code. With this proliferation of electronics the risk due to electronics failures are also increasing rapidly. Failures in electronics of these vehicles may have a hazardous affect on the vehicle. Consequences of failures associated with automobile electronics include accidents and recalls.
Automobile makers face a difficult task of assuring the safety and reliability of the electronic components of their vehicles. Today most makers rely on electrical testing of their systems which is very costly, time consuming, and cannot cover all the possible fault conditions and their potential impact on the system.
Conventional computer aided design (CAD) fault simulators may be used to introduce fault elements as changes into the design description. However, because of limited ability of the user to interact with the simulation during runtime, every design change requires time consuming recompilation of the simulation. Robust fault simulation capability within the simulation environment is needed so that designers and verification engineers may simulate different types of faults and understand the impact of faults before prototypes for physical testing are built.